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SubjectRe: [PATCH v1 2/4] dt-bindings: net: dsa: qca,ar9331 switch documentation
On Mon, Oct 14, 2019 at 08:15:47AM +0200, Oleksij Rempel wrote:
> Atheros AR9331 has built-in 5 port switch. The switch can be configured
> to use all 5 or 4 ports. One of built-in PHYs can be used by first built-in
> ethernet controller or to be used directly by the switch over second ethernet
> controller.
>
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> .../devicetree/bindings/net/dsa/ar9331.txt | 155 ++++++++++++++++++
> 1 file changed, 155 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/dsa/ar9331.txt
>
> diff --git a/Documentation/devicetree/bindings/net/dsa/ar9331.txt b/Documentation/devicetree/bindings/net/dsa/ar9331.txt
> new file mode 100644
> index 000000000000..b0f95fd19584
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dsa/ar9331.txt
> @@ -0,0 +1,155 @@
> +Atheros AR9331 built-in switch
> +=============================
> +
> +It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
> +MDIO bus. All PHYs are build-in as well.
> +
> +Required properties:
> +
> + - compatible: should be: "qca,ar9331-switch"
> + - reg: Address on the MII bus for the switch.
> + - resets : Must contain an entry for each entry in reset-names.
> + - reset-names : Must include the following entries: "switch"
> + - interrupt-parent: Phandle to the parent interrupt controller
> + - interrupts: IRQ line for the switch
> + - interrupt-controller: Indicates the switch is itself an interrupt
> + controller. This is used for the PHY interrupts.
> + - #interrupt-cells: must be 1
> + - mdio: Container of PHY and devices on the switches MDIO bus.
> +
> +See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
> +required and optional properties.
> +Examples:
> +
> +eth0: ethernet@19000000 {
> + compatible = "qca,ar9330-eth";
> + reg = <0x19000000 0x200>;
> + interrupts = <4>;
> +
> + resets = <&rst 9>, <&rst 22>;
> + reset-names = "mac", "mdio";
> + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
> + clock-names = "eth", "mdio";
> +
> + phy-mode = "mii";
> + phy-handle = <&phy_port4>;

This does not seem like a valid example. If phy_port4 is listed here,
i would expect switch_port 5 to be totally missing?

> +};
> +
> +eth1: ethernet@1a000000 {
> + compatible = "qca,ar9330-eth";
> + reg = <0x1a000000 0x200>;
> + interrupts = <5>;
> + resets = <&rst 13>, <&rst 23>;
> + reset-names = "mac", "mdio";
> + clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
> + clock-names = "eth", "mdio";
> +
> + phy-mode = "gmii";
> + phy-handle = <&switch_port0>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };

You also cannot have both a fixed-link and a phy-handle.

> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch10: switch@10 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compatible = "qca,ar9331-switch";
> + reg = <16>;

Maybe don't mix up hex and decimal? switch16: switch@16.

Andrew

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