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Subject[PATCH v2 3/4] perf/x86/intel: implement LBR callstacks context synchronization
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Implement intel_pmu_lbr_sync_task_ctx() method that updates counter
of the events that requested LBR callstack data on a sample.

The counter can be zero for the case when task context belongs to
a thread that has just come from a block on a futex and the context
contains saved (lbr_stack_state == LBR_VALID) LBR register values.

For the values to be restored at LBR registers on the next thread's
switch-in event it copies the counter value that is expected to be
non zero from the previous equivalent task perf event context.

Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com>
---
arch/x86/events/intel/lbr.c | 9 +++++++++
arch/x86/events/perf_event.h | 3 +++
2 files changed, 12 insertions(+)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index ea54634eabf3..152a3f8b516a 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -417,6 +417,15 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
cpuc->last_log_id = ++task_ctx->log_id;
}

+void intel_pmu_lbr_sync_task_ctx(struct x86_perf_task_context *one,
+ struct x86_perf_task_context *another)
+{
+ if (!one || !another)
+ return;
+
+ one->lbr_callstack_users = another->lbr_callstack_users;
+}
+
void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a25e6d7eb87b..3e0087c06fc9 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1024,6 +1024,9 @@ void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr);

void intel_ds_init(void);

+void intel_pmu_lbr_sync_task_ctx(struct x86_perf_task_context *one,
+ struct x86_perf_task_context *another);
+
void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);

u64 lbr_from_signext_quirk_wr(u64 val);
--
2.20.1
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