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SubjectRe: [RFC PATCH 0/6] SMMUv3 PMCG IMP DEF event support
On 15/10/2019 19:00, Robin Murphy wrote:
> Hi John,
> On 30/09/2019 15:33, John Garry wrote:
>> This patchset adds IMP DEF event support for the SMMUv3 PMCG.
>> It is marked as an RFC as the method to identify the PMCG implementation
>> may be a quite disliked. And, in general, the series is somewhat
>> incomplete.
>> So the background is that the PMCG supports IMP DEF events, yet we
>> have no
>> method to identify the PMCG to know the IMP DEF events.
>> A method for identifying the PMCG implementation could be using
>> PMDEVARCH, but we cannot rely on this being set properly, as whether this
>> is implemented is not defined in SMMUv3 spec.
>> Another method would be perf event aliasing, but this method of event
>> matching is based on CPU id, which would not guarantee same
>> uniqueness as PMCG implementation.
>> Yet another method could be to continue using ACPI OEM ID in the IORT
>> code, but this does not scale. And it is not suitable if we ever add DT
>> support to the PMCG driver.
>> The method used in this series is based on matching on the parent SMMUv3
>> IIDR. We store this IIDR contents in the arm smmu structure as the first
>> element, which means that we don't have to expose SMMU APIs - this is
>> the part which may be disliked.
>> The final two patches switch the pre-existing PMCG model identification
>> from ACPI OEM ID to the same parent SMMUv3 IIDR matching.
>> For now, we only consider SMMUv3' nodes being the associated node for
>> PMCG.

Hi Robin,

> Two significant concerns right off the bat:
> - It seems more common than not for silicon designers to fail to
> implement IIDR correctly, so it's only a matter of time before
> inevitably needing to bring back some firmware-level identifier
> abstraction (if not already - does Hi161x have PMCGs?)

Maybe there's a way that we can switch to this method, and leave the
door open for an easy way to support firmware-level identifier again, if
ever needed. I'm not too pushed - this was secondary to just allowing
the PMCG driver know the associated SMMU model.

And, no, hi161x does not have any PMCGs.

> - This seems like a step in entirely the wrong direction for supporting

So to support PMCGs that reference a Named Component or Root Complex, I
thought that the IORT parsing code would have to do some secondary
lookup to the associated SMMU, through the Named Component or Root
Complex node.

What was your idea here?

Note: I do acknowledge that an overall issue is that we assume all PMCG
IMP DEF events are same for a given SMMU model.

> Interpreting the Node Reference is definitely a welcome improvement over
> matching table headers, but absent a truly compelling argument to the
> contrary, I'd rather retain the "PMCG model" abstraction in between that
> and the driver itself (especially since those can trivially be hung off
> compatibles once it comes to DT support).

For DT, I would assume that we just use compatible strings would allow
us to identify the PMCG model.

On a related matter, is there still a need to deal with scenarios of the
PMCG being located within the SMMU register map? As you may remember, we
did have this issue but relocated the PMCG to outside the SMMU register
map in a later chip rev.


> Thanks,
> Robin.
>> John Garry (6):
>> ACPI/IORT: Set PMCG device parent
>> iommu/arm-smmu-v3: Record IIDR in arm_smmu_device structure
>> perf/smmuv3: Retrieve parent SMMUv3 IIDR
>> perf/smmuv3: Support HiSilicon hip08 (hi1620) IMP DEF events
>> perf/smmuv3: Match implementation options based on parent SMMU IIDR
>> ACPI/IORT: Drop code to set the PMCG software-defined model
>> drivers/acpi/arm64/iort.c | 69 ++++++++++++++--------------
>> drivers/iommu/arm-smmu-v3.c | 5 +++
>> drivers/perf/arm_smmuv3_pmu.c | 84 ++++++++++++++++++++++++++++++-----
>> include/linux/acpi_iort.h | 8 ----
>> 4 files changed, 112 insertions(+), 54 deletions(-)
> .

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