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Subject[PATCH v1 00/17] NVIDIA Tegra20 CPUFreq driver major update

This series moves intermediate-clk handling from tegra20-cpufreq into
tegra-clk driver, this allows us to switch to generic cpufreq-dt driver
which brings voltage scaling, per-hardware OPPs and Tegra30 support out
of the box. All boards need to adopt CPU OPPs in their device-trees in
order to get cpufreq support. This series adds OPPs only to selective
boards because there is assumption in a current device-trees that CPU
voltage is set for 1GHz freq and this won't work for those CPUs that
can go over 1GHz and thus require voltage regulators to be set up for
voltage scaling support (CC'ed Marcel for Toradex boards). We could
probably add delete-node for OPPs over 1GHz if there are not actively
maintained boards.

NOTE: the voltage scaling functionality depends on a reviewed and yet
unapplied series [0].


Dmitry Osipenko (17):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Support custom CCLK implementation
clk: tegra30: Support custom CCLK implementation
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
ARM: tegra: Remove tegra20-cpufreq platform device creation
ARM: dts: tegra20: Add CPU clock
ARM: dts: tegra30: Add CPU clock
ARM: dts: tegra20: Add CPU Operating Performance Points
ARM: dts: tegra30: Add CPU Operating Performance Points
ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS
ARM: dts: tegra20: paz00: Add CPU Operating Performance Points
ARM: dts: tegra20: trimslice: Add CPU Operating Performance Points
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points

.../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +
.../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 201 +++
arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 302 +++++
arch/arm/boot/dts/tegra20-paz00.dts | 41 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 11 +
arch/arm/boot/dts/tegra20.dtsi | 2 +
arch/arm/boot/dts/tegra30-beaver.dts | 40 +-
.../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 801 +++++++++++
arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 1202 +++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 4 +
arch/arm/mach-tegra/tegra.c | 4 -
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-pll.c | 12 +-
drivers/clk/tegra/clk-tegra-super-cclk.c | 165 +++
drivers/clk/tegra/clk-tegra20.c | 6 +-
drivers/clk/tegra/clk-tegra30.c | 6 +-
drivers/clk/tegra/clk.h | 12 +
drivers/cpufreq/Kconfig.arm | 4 +-
drivers/cpufreq/cpufreq-dt-platdev.c | 2 +
drivers/cpufreq/tegra20-cpufreq.c | 236 +---
20 files changed, 2902 insertions(+), 206 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi
create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp.dtsi
create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c


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