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SubjectRe: [PATCH 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420
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Hi Chanwoo,

On 1/29/19 1:54 AM, Chanwoo Choi wrote:
> Hi Lukasz,
>
> This patchset don't contain the cover-letter. Please send the
> cover-letter which explains what to do on this patchset.
>
> And is it supporting all Exynos5 for both 32bit(5420,5422)
> and 64bit(5433) or only Exynos542x(32bit)? If it only support
> the Exynos 542x series, you have to change the driver name
> from 'exynos5-dmc.c' to 'exynos5420-dmc.c' or 'exynos5422-dmc.c'
> in order to prevent the confusion according to the driver name.
I will rename the driver file to exynos5422-dmc.c and the config entry.
When the driver will get support for Exynos5433, the file name would
have to be changed again.

Regards,
Lukasz

>
>
> On 19. 1. 29. 오전 4:21, Lukasz Luba wrote:
>> Define new IDs for clocks used by Dynamic Memory Controller in
>> Exynos5422 SoC.
>>
>> CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> CC: Chanwoo Choi <cw00.choi@samsung.com>
>> CC: Rob Herring <robh+dt@kernel.org>
>> CC: Mark Rutland <mark.rutland@arm.com>
>> CC: Kukjin Kim <kgene@kernel.org>
>> CC: Krzysztof Kozlowski <krzk@kernel.org>
>> CC: linux-samsung-soc@vger.kernel.org
>> CC: devicetree@vger.kernel.org
>> CC: linux-arm-kernel@lists.infradead.org
>> CC: linux-kernel@vger.kernel.org
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
>> index 355f469..1827a64 100644
>> --- a/include/dt-bindings/clock/exynos5420.h
>> +++ b/include/dt-bindings/clock/exynos5420.h
>> @@ -60,6 +60,7 @@
>> #define CLK_MAU_EPLL 159
>> #define CLK_SCLK_HSIC_12M 160
>> #define CLK_SCLK_MPHY_IXTAL24 161
>> +#define CLK_SCLK_BPLL 162
>>
>> /* gate clocks */
>> #define CLK_UART0 257
>> @@ -195,6 +196,16 @@
>> #define CLK_ACLK432_CAM 518
>> #define CLK_ACLK_FL1550_CAM 519
>> #define CLK_ACLK550_CAM 520
>> +#define CLK_CLKM_PHY0 521
>> +#define CLK_CLKM_PHY1 522
>> +#define CLK_ACLK_PPMU_DREX0_0 523
>> +#define CLK_ACLK_PPMU_DREX0_1 524
>> +#define CLK_ACLK_PPMU_DREX1_0 525
>> +#define CLK_ACLK_PPMU_DREX1_1 526
>> +#define CLK_PCLK_PPMU_DREX0_0 527
>> +#define CLK_PCLK_PPMU_DREX0_1 528
>> +#define CLK_PCLK_PPMU_DREX1_0 529
>> +#define CLK_PCLK_PPMU_DREX1_1 530
>>
>> /* mux clocks */
>> #define CLK_MOUT_HDMI 640
>> @@ -217,6 +228,10 @@
>> #define CLK_MOUT_EPLL 657
>> #define CLK_MOUT_MAU_EPLL 658
>> #define CLK_MOUT_USER_MAU_EPLL 659
>> +#define CLK_MOUT_DPLL 660
>> +#define CLK_MOUT_ACLK_G3D 661
>> +#define CLK_MOUT_SCLK_SPLL 662
>> +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 663
>>
>> /* divider clocks */
>> #define CLK_DOUT_PIXEL 768
>> @@ -248,8 +263,9 @@
>> #define CLK_DOUT_CCLK_DREX0 794
>> #define CLK_DOUT_CLK2X_PHY0 795
>> #define CLK_DOUT_PCLK_CORE_MEM 796
>> +#define CLK_FF_DOUT_SPLL2 797
>>
>> /* must be greater than maximal clock id */
>> -#define CLK_NR_CLKS 797
>> +#define CLK_NR_CLKS 798
>>
>> #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
>>
>
>

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