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SubjectRE: [PATCH V5 3/5] i2c: tegra: Add DMA Support
Date
[Correction]

> > Could you please tell whether you missed my comments to V3 [0] or chose to ignore them? If the former, then I'd want to get answers to those questions and comments. I'll stop here for now.
> >
> > [0] https://patchwork.ozlabs.org/patch/1031379/
>
> Somehow missed those from multiple comments. Will go thru and respond back.

V6 includes feedback changes. Want to clarify on few feedback points

- ALIGN is used for 4 byte boundary to use with DMA but extra bytes doesn’t get transferred over I2C as I2C controller transfer bytes based on size specified in the packet header.
DMA length and memory address need to be 4 byte boundary.

- RX channel releasing when TX init fails?
For I2C both TX and RX doesn’t happen in same transaction and no dependency.
So if RX channel request & buffer allocation succeeds but TX channel request fails, then RX DMA can still be used for Msg reads and transmits can happen on PIO mode

- dma_burst < 8 negatively affects transfer efficiency? Performance stats for DMA Vs PIO mode.
Tested with 256 bytes of transfer and DMA Vs PIO mode transfer rate is almost same.
But the main reason for adding DMA mode is to address couple of cases mentioned earlier and not mainly from the transfer performance perspective.


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