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SubjectRe: [PATCH V5 3/5] i2c: tegra: Add DMA Support
В Tue, 29 Jan 2019 15:16:09 -0800
Sowjanya Komatineni <skomatineni@nvidia.com> пишет:

> This patch adds DMA support for Tegra I2C.
>
> Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> transfer size of the max FIFO depth and DMA mode is used for
> transfer size higher than max FIFO depth to save CPU overhead.
>
> PIO mode needs full intervention of CPU to fill or empty FIFO's
> and also need to service multiple data requests interrupt for the
> same transaction. This adds delay between data bytes of the same
> transfer when CPU is fully loaded and some slave devices has
> internal timeout for no bus activity and stops transaction to
> avoid bus hang. DMA mode is helpful in such cases.
>
> DMA mode is also helpful for Large transfers during downloading or
> uploading FW over I2C to some external devices.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> [V5] : Same as V4
> [V4] : Updated to allocate DMA buffer only when DMA mode.
> Updated to fall back to PIO mode when DMA channel request or
> buffer allocation fails.
> [V3] : Updated without additional buffer allocation.
> [V2] : Updated based on V1 review feedback along with code cleanup
> for proper implementation of DMA.

Could you please tell whether you missed my comments to V3 [0] or chose
to ignore them? If the former, then I'd want to get answers to those
questions and comments. I'll stop here for now.

[0] https://patchwork.ozlabs.org/patch/1031379/

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