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SubjectRe: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock
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Quoting Paul Cercueil (2019-01-25 07:34:36)
> The UDC clock is gated when the bit is cleared, not when it is set.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Artur Rojek <contact@artur-rojek.eu>
> ---

Any Fixes tag for this?

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