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SubjectRe: Question about qspinlock nest
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Hi Longman, Zhenzhong,

On 10/01/2019 14:43, Waiman Long wrote:
> On 01/10/2019 03:02 AM, Zhenzhong Duan wrote:
>> There is a question confused me for days. Appreciate an answer.
>>
>> In below code, the comment says we never have more than 4 nested
>> contexts.
>>
>> What happen if debug and mce exceptions nest with the four, or we
>> ensure it never happen?
>>
>>
>> /*
>>  * Per-CPU queue node structures; we can never have more than 4 nested
>>  * contexts: task, softirq, hardirq, nmi.
>>  *
>>  * Exactly fits one 64-byte cacheline on a 64-bit architecture.
>>  *
>>  * PV doubles the storage and uses the second cacheline for PV state.
>>  */
>> static DEFINE_PER_CPU_ALIGNED(struct qnode, qnodes[MAX_NODES]);

> Yes, both debug and mce exceptions are some kind of NMIs. So
> theoretically, it is possible to have more than four. Are you aware of
> any debug and MCE exception handlers that need to take a spinlock for
> synchronization?

On arm64 if all the RAS and psuedo-NMI patches land, our worst-case interleaving
jumps to at least 7. The culprit is APEI using spinlocks to protect fixmap slots.

I have an RFC to bump the number of node bits from 2 to 3, but as this is APEI
four times, it may be preferable to make it use something other than spinlocks.


The worst-case order is below. Each one masks those before it:
1. process context
2. soft-irq
3. hard-irq
4. psuedo-nmi [0]
- using the irqchip priorities to configure some IRQs as NMI.
5. SError [1]
- a bit like an asynchronous MCE. ACPI allows this to convey CPER records,
requiring an APEI call.
6&7. SDEI [2]
- a firmware triggered software interrupt, only its two of them, either of
which could convey CPER records.
8. Synchronous external abort
- again, similar to MCE. There are systems using this with APEI.


Thanks,

James


[0] lore.kernel.org/r/1546956464-48825-1-git-send-email-julien.thierry@arm.com
[1]
https://lore.kernel.org/r/1527770506-8076-1-git-send-email-gengdongjiu@huawei.com
[2]
https://lore.kernel.org/linux-arm-kernel/20181203180613.228133-26-james.morse@arm.com/

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