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Subject[PATCH V3 0/6] perf/core and x86/intel_rdt: Fix lack of coordination with perf
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Dear Maintainers,

This new series fixing the lack of coordination between the
pseudo-locking measurement code and perf addresses all feedback received
for V2.

Changes since V2:
- Move the helper to obtain the performance counter index to
include/linux/perf_event.h. The request was actually to move this helper
to arch/x86/include/asm/perf_event.h - but doing so would be more
involved since this header file does not know about struct perf_event
that is used by this helper. There was no response for further
clarification of the request to move this helper so I proceeded to move it
to include/linux/perf_event.h instead.
- Change name of helper to obtain the index to perf_rdpmc_index() - the
original request was to name it x86_perf_rdpmc_index() but this seems to
be tied to the suggested header location. With the header location of
include/linux/perf_event.h the name perf_rdpmc_index() seems to fit
better with the new destination. There was no response for further
clarification of the naming change request so I proceeded with the change.
- Replace all local register variables used in the measurement routines
with local variables using READ_ONCE().
- The removal of local register variables also enable us to replace the
direct __wrmsr() with wrmsr().
- Merge the L2 and L3 measurement routines following Peter's suggested
framework.
- Do not copy the text from SDM that refers to serializing instructions.
- Include another LFENCE call after loop reading pseudo-locked memory.

The above addresses all feedback received for V2. The one unanswered
question that remains following the review is why the memory reading
was done with asm: the reason I did so was to avoid any compiler
optimizations while constraining the code exactly to what needed to be
measured. By using the asm instruction I am able to use a single instruction
to read a cache line into a register. To me this seemed the most constrained
way to measure if a cache line is in the cache.

- Below is verbatim from V2 submission (except for diffstat below) -

This is the second attempt at fixing the lack of coordination between the
pseudo-locking measurement code and perf. Thank you very much for your
feedback on the first version. The entire solution, including the cover
letter, has been reworked based on your feedback, while submitted as a V2,
none of the patches from V1 remained.

Changes since V1:
- Use in-kernel interface to perf.
- Do not write directly to PMU registers.
- Do not introduce another PMU owner. perf maintains role as performing
resource arbitration for PMU.
- User space is able to use perf and resctrl at the same time.
- event_base_rdpmc is accessed and used only within an interrupts
disabled section.
- Internals of events are never accessed directly, inline function used.
- Due to "pinned" usage the scheduling of event may have failed. Error
state is checked in recommended way and have a credible error
handling.
- use X86_CONFIG

This code is based on the x86/cache branch of tip.git

The success of Cache Pseudo-Locking, as measured by how many cache lines
from a physical memory region has been locked to cache, can be measured
via the use of hardware performance events. Specifically, the number of
cache hits and misses reading a memory region after it has been
pseudo-locked to cache. This measurement is triggered via the resctrl
debugfs interface.

The current solution accesses performance counters and their configuration
registers directly without coordination with other performance event users
(perf).
Two of the issues that exist with the current solution:
- By writing to the performance monitoring registers directly a new owner
for these resources is introduced. The perf infrastructure already exist
to perform resource arbitration and the in-kernel infrastructure should
be used to do so.
- The current lack of coordination with perf will have consequences any time
two users, for example perf and cache pseudo-locking, attempt to do any
kind of measurement at the same time.

In this series the measurement of Cache Pseudo-Lock regions is moved to use
the in-kernel interface to perf. During the rework of the measurement
function the L2 and L3 cache measurements are separated to avoid the
additional code needed to decide on which measurement causing unrelated
cache hits and misses.

Your feedback on this work will be greatly appreciated.

Reinette

Reinette Chatre (6):
perf/core: Add sanity check to deal with pinned event failure
perf/core: Add helper to obtain performance counter index
x86/intel_rdt: Remove local register variables
x86/intel_rdt: Create required perf event attributes
x86/intel_rdt: Use perf infrastructure for measurements
x86/intel_rdt: Re-enable pseudo-lock measurements

Documentation/x86/intel_rdt_ui.txt | 22 +-
arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c | 365 +++++++++++---------
include/linux/perf_event.h | 26 +-
kernel/events/core.c | 6 +
4 files changed, 255 insertions(+), 164 deletions(-)

--
2.17.0

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