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SubjectRE: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf
> So _why_ doesn't this work? As said by Tony, that first call should
> prime the caches, so the second and third calls should not generate any
> misses.

How much code/data is involved? If there is a lot, then you may be unlucky
with cache coloring and the later parts of the "prime the caches" code path
may evict some lines loaded in the early parts.


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