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SubjectRe: [PATCH v12 3/3] tracing: Centralize preemptirq tracepoints and unify their usage
On Wed, 8 Aug 2018 07:33:10 -0700
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com> wrote:

> On Wed, Aug 08, 2018 at 09:07:24AM -0400, Steven Rostedt wrote:
> > On Wed, 8 Aug 2018 06:03:02 -0700
> > "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> wrote:
> >
> > > What's wrong with a this_cpu_inc()? It's atomic for the CPU. Although
> > > > it wont be atomic for the capture of the idx. But I also don't see
> > > > interrupts being disabled, thus an NMI is no different than any
> > > > interrupt doing the same thing, right?
> > >
> > > On architectures without increment-memory instructions, if you take an NMI
> > > between the load from sp->sda->srcu_lock_count and the later store, you
> > > lose a count. Note that both __srcu_read_lock() and __srcu_read_unlock()
> > > do increments of different locations, so you cannot rely on the usual
> > > "NMI fixes up before exit" semantics you get when incrementing and
> > > decrementing the same location.
> >
> > And how is this handled in the interrupt case? Interrupts are not
> > disabled here.
>
> Actually, on most architectures interrupts are in fact disabled:
>
> #define this_cpu_generic_to_op(pcp, val, op) \
> do { \
> unsigned long __flags; \
> raw_local_irq_save(__flags); \
> raw_cpu_generic_to_op(pcp, val, op); \
> raw_local_irq_restore(__flags); \
> } while (0)
>
> NMIs, not so much.

And do these archs have NMIs?

-- Steve

>
> > I would also argue that architectures without increment-memory
> > instructions shouldn't have NMIs ;-)
>
> I would also argue a lot of things, but objective reality does not take my
> opinions into account all that often. Which might be a good thing. ;-)
>
> Thanx, Paul

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