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SubjectRe: [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu <songjun.wu@linux.intel.com> wrote:
>
> From: Yixin Zhu <yixin.zhu@linux.intel.com>
>
> This patch adds binding documentation for grx500 clock controller.
>
> Signed-off-by: YiXin Zhu <yixin.zhu@linux.intel.com>
> Signed-off-by: Songjun Wu <songjun.wu@linux.intel.com>
> ---
>
> Changes in v2:
> - Rewrite clock driver's dt-binding document according to Rob Herring's
> comments.
> - Simplify device tree docoment, remove some clock description.
>
> .../devicetree/bindings/clock/intel,grx500-clk.txt | 39 ++++++++++++++++++++++

Please match the compatible string: intel,grx500-cgu.txt

> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
> new file mode 100644
> index 000000000000..e54e1dad9196
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,grx500-clk.txt
> @@ -0,0 +1,39 @@
> +Device Tree Clock bindings for grx500 PLL controller.
> +
> +This binding uses the common clock binding:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The grx500 clock controller supplies clock to various controllers within the
> +SoC.
> +
> +Required properties for clock node
> +- compatible: Should be "intel,grx500-cgu".
> +- reg: physical base address of the controller and length of memory range.
> +- #clock-cells: should be 1.
> +
> +Optional Propteries:
> +- intel,osc-frequency: frequency of the osc clock.
> +if missing, driver will use clock rate defined in the driver.

This should use a fixed-clock node instead.

> +
> +Example: Clock controller node:
> +
> + cgu: cgu@16200000 {
> + compatible = "intel,grx500-cgu", "syscon";
> + reg = <0x16200000 0x200>;
> + #clock-cells = <1>;
> + };
> +
> +
> +Example: UART controller node that consumes the clock generated by clock
> + controller.
> +
> + asc0: serial@16600000 {
> + compatible = "lantiq,asc";
> + reg = <0x16600000 0x100000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
> + clock-names = "freq", "asc";
> + };
> --
> 2.11.0
>

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