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Subject[GIT PULL] irqchip updates for 4.19
Hi Thomas,

The 4.19 PR is more of a GICv3 special than an actual irqchip PR.

It reworks the way we allocate LPIs so that it can be much more fine
grained (instead of the allocation in chunks of 32 interrupts that
we've used so far). This allows supporting system that have thousands
of devices (not kidding!), each one using a single MSI... It also helps in
situation where the hypervisor enforces a very small number of
available LPIs.

Another change is the conversion of the ITS driver to using raw
spinlocks, making it work on RT (yay!).

Please pull,


The following changes since commit 9d3cce1e8b8561fed5f383d22a4d6949db4eadbe:

Linux 4.18-rc5 (2018-07-15 12:49:31 -0700)

are available in the Git repository at:

git:// tags/irqchip-4.19

for you to fetch changes up to a8db74564b0c634667e1722264bde303d296f566:

irqchip/gic-v3-its: Make its_lock a raw_spin_lock_t (2018-08-06 09:16:19 +0100)

irqchip updates for 4.19

- GICv3 ITS LPI allocation revamp
- GICv3 support for hypervisor-enforced LPI range
- GICv3 ITS conversion to raw spinlock

Marc Zyngier (7):
irqchip/gic-v3-its: Refactor LPI allocator
irqchip/gic-v3-its: Use full range of LPIs
irqchip/gic-v3-its: Move minimum LPI requirements to individual busses
irqchip/gic-v3-its: Drop chunk allocation compatibility
irqchip/gic-v3: Expose GICD_TYPER in the rdist structure
irqchip/gic-v3-its: Honor hypervisor enforced LPI range
irqchip/gic-v3-its: Reduce minimum LPI allocation to 1 for PCI devices

Sebastian Andrzej Siewior (1):
irqchip/gic-v3-its: Make its_lock a raw_spin_lock_t

drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c | 3 +
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 16 +-
drivers/irqchip/irq-gic-v3-its-platform-msi.c | 2 +
drivers/irqchip/irq-gic-v3-its.c | 243 +++++++++++++++++---------
drivers/irqchip/irq-gic-v3.c | 4 +-
include/linux/irqchip/arm-gic-v3.h | 3 +-
6 files changed, 178 insertions(+), 93 deletions(-)

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