Messages in this thread |  | | Date | Mon, 27 Aug 2018 18:39:36 +0900 | From | Masami Hiramatsu <> | Subject | Re: TLB flushes on fixmap changes |
| |
On Mon, 27 Aug 2018 10:13:29 +0200 Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, Aug 27, 2018 at 12:03:05PM +0900, Masami Hiramatsu wrote: > > On Sun, 26 Aug 2018 11:09:58 +0200 > > Peter Zijlstra <peterz@infradead.org> wrote: > > > > FWIW, before text_poke_bp(), text_poke() would only be used from > > > stop_machine, so all the other CPUs would be stuck busy-waiting with > > > IRQs disabled. These days, yeah, that's lots more dodgy, but yes > > > text_mutex should be serializing all that. > > > > I'm still not sure that speculative page-table walk can be done > > over the mutex. Also, if the fixmap area is for aliasing > > pages (which always mapped to memory), what kind of > > security issue can happen? > > So suppose CPU-A is doing the text_poke (let's say through text_poke_bp, > such that other CPUs get to continue with whatever they're doing). > > While at that point, CPU-B gets an interrupt, and the CPU's > branch-trace-buffer for the IRET points to / near our fixmap. Then the > CPU could do a speculative TLB fill based on the BTB value, either > directly or indirectly (through speculative driven fault-ahead) of > whatever is in te fixmap at the time.
Hmm, but how "near" is it enough? Since text_poke just map a non executable alias page in fixmap, it is hard to suppose that IRET points there (except for attacker change the IRET address).
I see that Intel CPU sometimes speculatively read-ahead the page tables, but in that case, I guess we just need to keep fixmap area away from text area. (Of course, it is hard to estimate how far is enough :( )
Anyway, I agree to introduce new page-table (and kthread?) for fixmap.
> Then CPU-A completes the text_poke and only does a local TLB invalidate > on CPU-A, leaving CPU-B with an active translation. > > *FAIL*
Ah, I got it. So on CPU-B, it can write-access to fixmap'd pages unless the CPU-B shoot down the full TLB...
Thank you,
-- Masami Hiramatsu <mhiramat@kernel.org>
|  |