lkml.org 
[lkml]   [2018]   [Aug]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH 2/2] clk: qcom: Add camera clock controller driver for SDM845
Date
Quoting Amit Nischal (2018-07-30 00:20:52)
> On 2018-07-26 22:52, Stephen Boyd wrote:
> > Quoting Amit Nischal (2018-07-23 04:26:33)
> >> diff --git a/drivers/clk/qcom/camcc-sdm845.c
> >> b/drivers/clk/qcom/camcc-sdm845.c
> >> new file mode 100644
> >> index 0000000..61e5ec2
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/camcc-sdm845.c
> >> +static struct clk_rcg2 cam_cc_bps_clk_src = {
> >> + .cmd_rcgr = 0x600c,
> >> + .mnd_width = 0,
> >> + .hid_width = 5,
> >> + .parent_map = cam_cc_parent_map_0,
> >> + .freq_tbl = ftbl_cam_cc_bps_clk_src,
> >> + .clkr.hw.init = &(struct clk_init_data){
> >> + .name = "cam_cc_bps_clk_src",
> >> + .parent_names = cam_cc_parent_names_0,
> >> + .num_parents = 6,
> >> + .flags = CLK_SET_RATE_PARENT,
> >> + .ops = &clk_rcg2_shared_ops,
> >
> > Why are shared ops used in this driver?
> >
>
> As per HW design, most of the CAMCC RCGs needs to move to
> XO during clock disable so because of this we have used the
> shared ops.

Please add a comment to this effect in this driver and also mention this
in the commit text. I guess the camera firmware is also doing clk
control and so it wants the clk to be on at some basic rate in case
that's happening?

> >> +
> >> +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
> >> + .cmd_rcgr = 0x6054,
> >> + .mnd_width = 0,
> >> + .hid_width = 5,
> >> + .parent_map = cam_cc_parent_map_0,
> >> + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
> >> + .clkr.hw.init = &(struct clk_init_data){
> >> + .name = "cam_cc_slow_ahb_clk_src",
> >> + .parent_names = cam_cc_parent_names_0,
> >> + .num_parents = 6,
> >> + .flags = CLK_SET_RATE_PARENT,
> >
> > Is CLK_SET_RATE_PARENT intentionally set on these RCGs so that they can
> > reconfigure the PLL frequency? Wouldn't that be a fixed rate PLL
> > frequency?
> >
>
> PLL2_OUT_EVEN requires to be reconfigure to 480MHz so clock sources
> which
> are using PLL2 in their frequency table requires 'CLK_SET_RATE_PARENT'
> flag to be set.

Ok.

\
 
 \ /
  Last update: 2018-08-02 18:58    [W:0.048 / U:5.780 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site