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SubjectRe: [PATCH net-next 01/10] MIPS: mscc: ocelot: make HSIO registers address range a syscon
On 30/07/2018 14:43:46+0200, Quentin Schulz wrote:
> HSIO contains registers for PLL5 configuration, SerDes/switch port
> muxing and a thermal sensor, hence we can't keep it in the switch DT
> node.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

> ---
> arch/mips/boot/dts/mscc/ocelot.dtsi | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> index afe8fc9..c51663a 100644
> --- a/arch/mips/boot/dts/mscc/ocelot.dtsi
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -96,7 +96,6 @@
> reg = <0x1010000 0x10000>,
> <0x1030000 0x10000>,
> <0x1080000 0x100>,
> - <0x10d0000 0x10000>,
> <0x11e0000 0x100>,
> <0x11f0000 0x100>,
> <0x1200000 0x100>,
> @@ -110,10 +109,10 @@
> <0x1280000 0x100>,
> <0x1800000 0x80000>,
> <0x1880000 0x10000>;
> - reg-names = "sys", "rew", "qs", "hsio", "port0",
> - "port1", "port2", "port3", "port4", "port5",
> - "port6", "port7", "port8", "port9", "port10",
> - "qsys", "ana";
> + reg-names = "sys", "rew", "qs", "port0", "port1",
> + "port2", "port3", "port4", "port5", "port6",
> + "port7", "port8", "port9", "port10", "qsys",
> + "ana";
> interrupts = <21 22>;
> interrupt-names = "xtr", "inj";
>
> @@ -220,5 +219,10 @@
> pinctrl-0 = <&miim1>;
> status = "disabled";
> };
> +
> + hsio: syscon@10d0000 {
> + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
> + reg = <0x10d0000 0x10000>;
> + };
> };
> };
> --
> git-series 0.9.1

--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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