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    Subject[PATCH v12 03/13] x86/sgx: add SGX definitions to msr-index.h
    Date
    From: Sean Christopherson <sean.j.christopherson@intel.com>

    ENCLS and ENCLU are usable if and only if SGX_ENABLE is set and After
    SGX is activated the IA32_SGXLEPUBKEYHASHn MSRs are writable if
    SGX_LC_WR is set and the feature control is locked.

    SGX related bits in IA32_FEATURE_CONTROL cannot be set before SGX is
    activated by the pre-boot firmware. SGX activation is triggered by
    setting bit 0 in the MSR 0x7a. Until SGX is activated, the LE hash MSRs
    are writable to allow pre-boot firmware to lock down the LE root key
    with a non-Intel value.

    Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
    Co-developed-by: Haim Cohen <haim.cohen@intel.com>
    ---
    arch/x86/include/asm/msr-index.h | 8 ++++++++
    1 file changed, 8 insertions(+)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index fda2114197b3..a7355fb7344f 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -479,6 +479,8 @@
    #define FEATURE_CONTROL_LOCKED (1<<0)
    #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
    #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
    +#define FEATURE_CONTROL_SGX_ENABLE (1<<18)
    +#define FEATURE_CONTROL_SGX_LE_WR (1<<17)
    #define FEATURE_CONTROL_LMCE (1<<20)

    #define MSR_IA32_APICBASE 0x0000001b
    @@ -545,6 +547,12 @@
    #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
    #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)

    +/* Intel SGX MSRs */
    +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
    +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
    +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
    +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
    +
    /* Thermal Thresholds Support */
    #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
    #define THERM_SHIFT_THRESHOLD0 8
    --
    2.17.1
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