lkml.org 
[lkml]   [2018]   [Jul]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
SubjectRe: [PATCH] NET: stmmac: align DMA stuff to largest cache line length
From
From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Thu, 26 Jul 2018 15:05:37 +0300

> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2 line. This
> can lead to sharing one cache line between DMA buffer and other
> data, so we can lose this data while invalidate DMA buffer before
> DMA transaction.
>
> Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
> aligning.
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

This is definitely an improvement, so applied and queued up for
-stable.

There is also dma_get_cache_alignment(), so maybe we can eventually
use that here instead.

\
 
 \ /
  Last update: 2018-07-29 21:36    [W:0.040 / U:0.036 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site