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SubjectRe: [PATCH] NET: stmmac: align DMA stuff to largest cache line length
From: Eugeniy Paltsev <>
Date: Thu, 26 Jul 2018 15:05:37 +0300

> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2 line. This
> can lead to sharing one cache line between DMA buffer and other
> data, so we can lose this data while invalidate DMA buffer before
> DMA transaction.
> Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
> aligning.
> Signed-off-by: Eugeniy Paltsev <>

This is definitely an improvement, so applied and queued up for

There is also dma_get_cache_alignment(), so maybe we can eventually
use that here instead.

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