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SubjectRe: [PATCH v2 2/2] PCI: NVMe device specific reset quirk
On Mon, 23 Jul 2018 19:20:41 -0700
Sinan Kaya <> wrote:

> On 7/23/18, Alex Williamson <> wrote:
> > On Mon, 23 Jul 2018 17:40:02 -0700
> > Sinan Kaya <> wrote:
> >
> >> On 7/23/2018 5:13 PM, Alex Williamson wrote:
> >> > + * The NVMe specification requires that controllers support PCIe FLR,
> >> > but
> >> > + * but some Samsung SM961/PM961 controllers fail to recover after FLR
> >> > (-1
> >> > + * config space) unless the device is quiesced prior to FLR.
> >>
> >> Does disabling the memory bit in PCI config space as part of the FLR
> >> reset function help? (like the very first thing)
> >
> > No, it does not. I modified this to only clear PCI_COMMAND_MEMORY and
> > call pcie_flr(), the Samsung controller dies just as it did previously.
> >
> >> Can we do that in the pcie_flr() function to cover other endpoint types
> >> that might be pushing traffic while code is trying to do a reset?
> >
> > Do you mean PCI_COMMAND_MASTER rather than PCI_COMMAND_MEMORY?
> Yes
> > I tried
> > that too, it doesn't work either. I'm not really sure the theory
> > behind clearing memory, clearing busmaster to stop DMA seems like a
> > sane thing to do, but doesn't help here.
> Let me explain what I guessed. You might be able to fill in the blanks
> where I am completely off.
> We do vfio initiated flr reset immediately following guest machine
> shutdown. The card could be fully enabled and pushing traffic to the
> system at this moment.
> I don't know if vfio does any device disable or not.

Yes, pci_clear_master() is the very first thing we do in
vfio_pci_disable(), well before we try to reset the device.

> FLR is supposed to reset the endpoint but endpoint doesn't recover per
> your report.
> Having vendor specific reset routines for PCIE endpoints defeats the
> purpose of FLR.
> Since the adapter is fully functional, i suggested turning off bus
> master and memory enable bits to stop endpoint from sending packets.
> But, this is not helping either.
> Those sleep statements looked very fragile to be honest.
> I was curious if there is something else that we could do for other endpoints.
> No objections otherwise.

I certainly agree that it would be nice if FLR was more robust on these
devices, but if all devices behaved within the specs we wouldn't have
these quirks to start with ;) Just as you're suggesting maybe we could
disable busmaster before FLR, which is reasonable but doesn't work
here, I'm basically moving that to a class specific action, quiesce the
controller at the NVMe level rather than PCI level. Essentially that's
why I thought it reasonable to apply to all NVMe class devices rather
than create just a quirk that delays after FLR for Intel and another
that disables the NVMe controller just for Samsung. Once I decide to
apply to the whole class, then I need to bring in the device specific
knowledge already found in the native nvme driver for the delay between
clearing the enable bit and checking the ready status bit. If it's
fragile, then the bare metal nvme driver has the same frailty. For the
delay I added, all I can say is that it works for me and improves the
usability of the device for this purpose. I know that 200ms is too
low, ISTR the issue was fixed at 210-220ms, so 250ms provides some
headroom and I've not seen any issues there. If we want to make it 500
or 1000ms, that's fine by me, I expect it'd work, it's just unnecessary
until we find devices that need longer delays. Thanks,


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