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Subject[PATCH 4.17 147/220] clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
4.17-stable review patch.  If anyone has any objections, please let me know.


From: Martin Blumenstingl <>

commit 72e1f2302040398dafb64bbb93abdde78c1f2267 upstream.

Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we
relied on the bootloader to enable the fclk_div clock gates. It turns
out that our clock tree is incomplete at least on Meson8b (tested with
an Odroid-C1, which uses an RGMII PHY) because after the mentioned
commit Ethernet is not working anymore (no RX/TX activity can be seen).
At the same time Ethernet was still working on Meson8m2 with a RMII PHY.

Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops
working on Odroid-C1. Unfortunately it's currently not clear what the
Ethernet controller IP block uses the fclk_div2 clock for. Mark the
clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by
most bootloaders by default, which is why we didn't notice it before).

Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Signed-off-by: Martin Blumenstingl <>
Tested-by: Kevin Hilman <>
Signed-off-by: Jerome Brunet <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/clk/meson/meson8b.c | 7 +++++++
1 file changed, 7 insertions(+)

--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -246,6 +246,13 @@ static struct clk_regmap meson8b_fclk_di
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "fclk_div2_div" },
.num_parents = 1,
+ /*
+ * FIXME: Ethernet with a RGMII PHYs is not working if
+ * fclk_div2 is disabled. it is currently unclear why this
+ * is. keep it enabled until the Ethernet driver knows how
+ * to manage this clock.
+ */
+ .flags = CLK_IS_CRITICAL,

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