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Subject[PATCH 4.17 101/220] mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally
4.17-stable review patch.  If anyone has any objections, please let me know.


From: Masahiro Yamada <>

commit 3f6e6986045d47f87bd982910821b7ab9758487e upstream.

Since commit 1bb88666775e ("mtd: nand: denali: handle timing parameters
by setup_data_interface()"), denali_dt.c gets the clock rate from the
clock driver. The driver expects the frequency of the bus interface
clock, whereas the clock driver of SOCFPGA provides the core clock.
Thus, the setup_data_interface() hook calculates timing parameters
based on a wrong frequency.

To make it work without relying on the clock driver, hard-code the clock
frequency, 200MHz. This is fine for existing DT of UniPhier, and also
fixes the issue of SOCFPGA because both platforms use 200 MHz for the
bus interface clock.

Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by setup_data_interface()")
Cc: linux-stable <> #4.14+
Reported-by: Philipp Rosenberger <>
Suggested-by: Boris Brezillon <>
Signed-off-by: Masahiro Yamada <>
Tested-by: Richard Weinberger <>
Signed-off-by: Boris Brezillon <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/mtd/nand/raw/denali_dt.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

--- a/drivers/mtd/nand/raw/denali_dt.c
+++ b/drivers/mtd/nand/raw/denali_dt.c
@@ -123,7 +123,11 @@ static int denali_dt_probe(struct platfo
if (ret)
return ret;

- denali->clk_x_rate = clk_get_rate(dt->clk);
+ /*
+ * Hardcode the clock rate for the backward compatibility.
+ * This works for both SOCFPGA and UniPhier.
+ */
+ denali->clk_x_rate = 200000000;

ret = denali_init(denali);
if (ret)

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