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Subject[PATCH 4.14 135/157] ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
4.14-stable review patch.  If anyone has any objections, please let me know.


From: Hans de Goede <>

commit fdcb613d49321b5bf5d5a1bd0fba8e7c241dcc70 upstream.

The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set
of private registers at offset 0x800, the current lpss_device_desc for
them already sets the LPSS_SAVE_CTX flag to have these saved/restored
over device-suspend, but the current lpss_device_desc was not setting
the prv_offset field, leading to the regular device registers getting
saved/restored instead.

This is causing the PWM controller to no longer work, resulting in a black
screen, after a suspend/resume on systems where the firmware clears the
APB clock and reset bits at offset 0x804.

This commit fixes this by properly setting prv_offset to 0x800 for
the PWM devices.

Fixes: e1c748179754 ("ACPI / LPSS: Add Intel BayTrail ACPI mode PWM")
Fixes: 1bfbd8eb8a7f ("ACPI / LPSS: Add ACPI IDs for Intel Braswell")
Signed-off-by: Hans de Goede <>
Acked-by: Rafael J . Wysocki <>
Signed-off-by: Thierry Reding <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/acpi/acpi_lpss.c | 2 ++
1 file changed, 2 insertions(+)

--- a/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@ -229,11 +229,13 @@ static const struct lpss_device_desc lpt

static const struct lpss_device_desc byt_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX,
+ .prv_offset = 0x800,
.setup = byt_pwm_setup,

static const struct lpss_device_desc bsw_pwm_dev_desc = {
+ .prv_offset = 0x800,
.setup = bsw_pwm_setup,

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