[lkml]   [2018]   [Jun]   [7]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v9 03/12] perf/x86/intel/pt: Add new bit definitions for Intel PT MSRs
On Tue, May 22, 2018 at 12:52:06PM +0800, Luwei Kang wrote:
> These bit definitions are use for emulate MSRs read/write
> for KVM. For example, IA32_RTIT_CTL.FabricEn[bit 6] is available
> only when CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 1. If KVM guest
> try to set this bit with CPUID.(EAX=14H, ECX=0):ECX[bit3] = 0
> a #GP would be injected to KVM guest.

Do we have anything in the guest that this feature will work with?


 \ /
  Last update: 2018-06-07 15:34    [W:0.130 / U:2.024 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site