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SubjectRe: [PATCH] gpio: zynq: Setup chip->base based on alias ID
On 2.5.2018 15:56, Linus Walleij wrote:
> On Wed, May 2, 2018 at 3:41 PM, Michal Simek <> wrote:
>> If you don't want this patch I understand that and it will become just
>> another soc vendor patch out of mainline.
> I don't really know what to do, so that is why I'm discussing.

me too. It is also interesting that I have met with the case with
zynq/zynqmp gpio driver and not gpio-xilinx.c which can have a lot of

> It's one of those gray areas.
> From one point of view there is the purist stance that we should
> only support what the mainline tree does, and be strict and
> consistent so we don't accumulate to many nasty hacks.

Also this expect that the first patch does everything right which is not
truth all the time.

> On the other hand, it is completely possible that all users of this
> particular driver actually must have this patch, and then I just
> push them to use a deviant vendor tree for no good reason.
> Would it be possible that I apply the patch, and somehow also
> establish some understanding with all users of the Xilinx
> platform that whatever legacy applications are out there
> must start to migrate towards using the character device so
> this reliance on the numberspace doesn't stick around forever?

When someone contacts me for asking guidance for gpio I am telling them
not to use legacy sysfs interface and use libgpiod. Last one was a week
ago in connection to Ultra96 and libmraa.

But even chardev is not supported there now.

> For example can we make a patch to some systems like
> arch/arm/boot/dts/zynq-*.dts
> adding proper GPIO line names to these device trees, such
> as was made in e.g. commit f6b1674d570aa1
> "arm64: dts: qcom: sbc: Name GPIO lines"

If you take a look at
which is Ultra96 board gpio-line-names are filled there for the whole PS
part. Definitely take a look and let know if you find out any issue there.

zynq/zynqmp gpio controller contains PS pins (hard part) and PL pins
coming to logic.

I can't describe PL gpio pins because it can be whatever even I have
done that for one fixed hw design.

Interesting part on that sha1 you shared is how "NC" pin is described.

gpio pin 35 I have on zcu100 as "" but it should be maybe TP_PAD which
is really just a pad on real board. And the rest of "" gpio names are
connected to PL.

I am happy to take a look at existing platforms and use gpio-line-names
there. For example arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
I use in tca6416_u97 and u61 comments instead of this property.

> After all that is what I strive for as maintainer, as the IETF
> motto says:
> "rough consensus and running code"


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