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SubjectRe: [PATCH 2/2] x86/mm: Introduce 'no5lvl' kernel parameter
On Sun, May 13, 2018 at 09:55:00PM +0000, Thomas Gleixner wrote:
> On Fri, 11 May 2018, Kirill A. Shutemov wrote:
> > --- a/arch/x86/kernel/cpu/common.c
> > +++ b/arch/x86/kernel/cpu/common.c
> > @@ -1008,6 +1008,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
> > */
> > setup_clear_cpu_cap(X86_FEATURE_PCID);
> > #endif
> > +
> > +#ifdef CONFIG_X86_5LEVEL
> > + /* Clear the 5-level paging feature if user asked for 'no5lvl' */
>
> no5lvl is only one reason why 5 level paging is not available.

The 5-level paging may not be available for few reasons:
- CONFIG_X86_5LEVEL=n
- Machine doesn't support X86_FEATURE_LA57 -- clearing is nop;
- User asked for 'no5lvl'.

To me the one-line comment reflects the situation reasonably well.

Do you want more verbose comment here?
> > + if (!__pgtable_l5_enabled)
> > + setup_clear_cpu_cap(X86_FEATURE_LA57);
> > +#endif
>
> And that #ifdeffery can be avoided by simply doing:
>
> if (IS_ENABLED(CONFIG_X86_5LEVEL) && !pgtable_l5_enabled)
> setup_clear_cpu_cap(X86_FEATURE_LA57);
>
> Hmm?

Unfortunately, no.

pgtable_l5_enabled is defined as cpu_feature_enabled(X86_FEATURE_LA57).
So with such change we would only clear the feature bit if it's already
clear.

--
Kirill A. Shutemov

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