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SubjectRe: [PATCH v5 06/23] iommu/vt-d: add definitions for PFSID
On Mon, 14 May 2018 09:36:08 +0800
Lu Baolu <baolu.lu@linux.intel.com> wrote:

> Hi,
>
> On 05/12/2018 04:53 AM, Jacob Pan wrote:
> > When SRIOV VF device IOTLB is invalidated, we need to provide
> > the PF source ID such that IOMMU hardware can gauge the depth
> > of invalidation queue which is shared among VFs. This is needed
> > when device invalidation throttle (DIT) capability is supported.
> >
> > This patch adds bit definitions for checking and tracking PFSID.
>
> Patch 6 and 7 could be posted in a separated patch series.
>
Thought about that also, but we need to include PFSID passdown
invalidation in this patchset, that is why i prefer to include
this fix, otherwise this patchset will continue to be wrong.
> >
> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > ---
> > include/linux/intel-iommu.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/include/linux/intel-iommu.h
> > b/include/linux/intel-iommu.h index ddc7d79..dfacd49 100644
> > --- a/include/linux/intel-iommu.h
> > +++ b/include/linux/intel-iommu.h
> > @@ -114,6 +114,7 @@
> > * Extended Capability Register
> > */
> >
> > +#define ecap_dit(e) ((e >> 41) & 0x1)
> > #define ecap_pasid(e) ((e >> 40) & 0x1)
> > #define ecap_pss(e) ((e >> 35) & 0x1f)
> > #define ecap_eafs(e) ((e >> 34) & 0x1)
> > @@ -284,6 +285,7 @@ enum {
> > #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
> > #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
> > #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) &
> > VTD_PAGE_MASK) +#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid &
> > 0xf) << 12) | ((u64)(pfsid & 0xff0) << 48)) #define
> > QI_DEV_IOTLB_SIZE 1 #define QI_DEV_IOTLB_MAX_INVS 32
> >
> > @@ -308,6 +310,7 @@ enum {
> > #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
> > #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
> > #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
> > +#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) |
> > ((u64)(pfsid & 0xff0) << 48))
>
> PFSID[15:4] are stored in Descriptor [63:52], hence it should look
> like:
>
> +#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) |
> ((u64)(pfsid & 0xfff0) << 48))
>
>
good catch! thanks.
>
> > #define QI_DEV_EIOTLB_MAX_INVS 32
> >
> > #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
> > @@ -467,6 +470,7 @@ struct device_domain_info {
> > struct list_head global; /* link to global list */
> > u8 bus; /* PCI bus number */
> > u8 devfn; /* PCI devfn number */
> > + u16 pfsid; /* SRIOV physical function
> > source ID */ u8 pasid_supported:3;
> > u8 pasid_enabled:1;
> > u8 pri_supported:1;
>
> Best regards,
> Lu Baolu

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