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SubjectRe: [PATCH] MIPS: c-r4k: fix data corruption related to cache coherence.
Hi NeilBrown,

On Wed, Apr 25, 2018 at 02:08:15PM +1000, NeilBrown wrote:
> Cc: (v4.8)

FYI my preferred form of this is:

Cc: <> # 4.8+

> /*
> * Either no secondary cache or the available caches don't have the
> * subset property so we have to flush the primary caches
> - * explicitly
> + * explicitly.
> + * As Index type operations are not globalized by CM, we must
> + * use the HIT type when CM is present.

I don't think Index type operations *can* be sensibly globalised to
separate primary caches, since they directly index the lines in the
cache rather than any particular physical or virtual address, so this
fundamental issue doesn't sound specific to the CM.

I'm not entirely clear OTOH whether there are any non-CM r4k-like SMP
capable cores that don't have coherent IO or inclusive caches.
- Octeon doesn't use c-r4k and has coherent IO
- Netlogic appear to have coherent IO
- Loongson64 have inclusive caches
- bmips, only bmips5000 appears to have multicore (not just multi-thread
with I presume shared dcaches), and that has inclusive caches

So I suppose that does just leave non-multicore and CM systems as
potentially reaching these bits of code...

> */
> - if (size >= dcache_size) {
> + if (!mips_cm_present() && size >= dcache_size) {

... but even for CM systems its only if there are foreign CPUs running
(i.e. not just threads on the same core sharing the same dcache) that it
actually matters.

So I'm thinking "!mips_cm_present()" should probably be replaced with
"!r4k_op_needs_ipi(R4K_INDEX)" (and the comment updated to mention that
IPI calls aren't implemented here).

That effectively means:
!CONFIG_SMP || cpumask_empty(&cpu_foreign_map[0])

Otherwise the patch looks spot on. Thanks for spotting this!

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