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SubjectRe: [PATCH 1/1] iommu/vt-d: Use real PASID for flush in caching mode
On Fri, Mar 16, 2018 at 12:31:36PM +0800, Lu Baolu wrote:
> If caching mode is supported, the hardware will cache
> none-present or erroneous translation entries. Hence,
> software should explicitly invalidate the PASID cache
> after a PASID table entry becomes present. We should
> issue such invalidation with the PASID value that we
> have changed. PASID 0 is not reserved for this case.
>
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Cc: Kevin Tian <kevin.tian@intel.com>
> Cc: Sankaran Rajesh <rajesh.sankaran@intel.com>
> Suggested-by: Ashok Raj <ashok.raj@intel.com>
> Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
> drivers/iommu/intel-svm.c | 16 ++++++----------
> 1 file changed, 6 insertions(+), 10 deletions(-)

Applied, thanks.

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