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Subject[PATCH 00/12] Major code reorganization to make all i2c transfers working
The current driver is failing in following test case
1. Handling of failure cases is not working in long run for BAM
mode. It generates error message “bam-dma-engine 7884000.dma: Cannot
free busy channel” sometimes.
2. Following I2C transfers are failing
a. Single transfer with multiple read messages
b. Single transfer with multiple read/write message with maximum
allowed length per message (65K) in BAM mode
c. Single transfer with write greater than 32 bytes in QUP v1 and
write greater than 64 bytes in QUP v2 for non-DMA mode.
3. No handling is present for Block/FIFO interrupts. Any non-error
interrupts are being treated as the transfer completion and then
polling is being done for available/free bytes in FIFO.

To fix all these issues, major code changes are required. This patch
series fixes all the above issues and makes the driver interrupt based
instead of polling based. After these changes, all the mentioned test
cases are working properly.

The code changes have been tested for QUP v1 (IPQ8064) and QUP
v2 (IPQ8074) with sample application written over i2c-dev.

Abhishek Sahu (12):
i2c: qup: fixed releasing dma without flush operation completion
i2c: qup: minor code reorganization for use_dma
i2c: qup: remove redundant variables for BAM SG count
i2c: qup: schedule EOT and FLUSH tags at the end of transfer
i2c: qup: fix the transfer length for BAM rx EOT FLUSH tags
i2c: qup: proper error handling for i2c error in BAM mode
i2c: qup: use the complete transfer length to choose DMA mode
i2c: qup: change completion timeout according to transfer length
i2c: qup: fix buffer overflow for multiple msg of maximum xfer len
i2c: qup: send NACK for last read sub transfers
i2c: qup: reorganization of driver code to remove polling for qup v1
i2c: qup: reorganization of driver code to remove polling for qup v2

drivers/i2c/busses/i2c-qup.c | 1538 +++++++++++++++++++++++++-----------------
1 file changed, 924 insertions(+), 614 deletions(-)

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