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Subject[PATCH v7 0/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer
Hi, all:

ATCPIT100 is often used on the Andes architecture,
This timer provide 4 PIT channels. Each PIT channel is a
multi-function timer, can be configured as 32,16,8 bit timers
or PWM as well.

For system timer it will set channel 1 32-bit timer0 as clock
source and count downwards until underflow and restart again.

It also set channel 0 32-bit timer0 as clock event and count
downwards until condition match. It will generate an interrupt
for handling periodically.

Changes in v7:
- Fix atcpit100_clkevt_next_event(), before set reload register,
clock source timer shall disable. And re-enable it after the setting.
Without this modification, the test case 'clock_nanosleep02' of ltp_20170929
will fail.

Changes in v6:
- To select TIMER_OF in drivers/clocksource/Kconfig instead of arch/nds32/Kconfig
- Refine Kconfig
- Update license format to SPDX-License-Identifier

Rick Chen (3):
clocksource/drivers/atcpit100: Add andestech atcpit100 timer
clocksource/drivers/atcpit100: VDSO support
dt-bindings: timer: Add andestech atcpit100 timer binding doc

.../bindings/timer/andestech,atcpit100-timer.txt | 33 +++
drivers/clocksource/Kconfig | 9 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-atcpit100.c | 266 +++++++++++++++++++++
4 files changed, 309 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
create mode 100644 drivers/clocksource/timer-atcpit100.c


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