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SubjectRe: [PATCH V6 4/9] clk: imx: add pfdv2 support
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Quoting A.s. Dong (2018-11-14 05:01:47)
> The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
> Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
>
> NOTE pfdv2 can only be operated when clk is gated.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Anson Huang <Anson.Huang@nxp.com>
> Cc: Bai Ping <ping.bai@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> ---

Applied to clk-next

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