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Subject[PATCHv3 2/4] arm64: dts: Add the PCIE EP node in dts
Date
Add the PCIE EP node in dts for ls1046a.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
v2:
- Add the SoC specific compatibles.
v3:
- no change

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 32 ++++++++++++++++++++++++
1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 8cfc848..c9ca9ed 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -657,6 +657,17 @@
status = "disabled";
};

+ pcie_ep@3400000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -683,6 +694,17 @@
status = "disabled";
};

+ pcie_ep@3500000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -709,6 +731,16 @@
status = "disabled";
};

+ pcie_ep@3600000 {
+ compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <6>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
};

reserved-memory {
--
1.7.1
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