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Subject[PATCH v9 23/27] MIPS: CI20: Reduce system timer to 3 MHz
Date
The default clock (48 MHz) is too fast for the system timer.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
v5: New patch

v6: Set also the rate for the clocksource channel's clock

v7: No change

v8: No change

v9: Don't configure clock timer1, as the OS Timer is used as
clocksource on this SoC

arch/mips/boot/dts/ingenic/ci20.dts | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 50cff3cbcc6d..700cf28a52ec 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -238,3 +238,9 @@
bias-disable;
};
};
+
+&tcu {
+ /* 3 MHz for the system timer */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>;
+ assigned-clock-rates = <3000000>;
+};
--
2.11.0
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