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SubjectRe: [PATCH v4 01/18] arm64: dts: qcom: qcs404: add base dts files
On 08-11-18, 15:45, Rob Herring wrote:
> > +/ {
> > + interrupt-parent = <&intc>;
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + chosen { };
> > +
> > + clocks {
> > + xo_board: xo_board {
>
> Build your dtbs with "W=12" and fix any warnings. You should get a
> warning about '_'.

I did built it with W=1 though, so _ is not allowed?

> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <19200000>;
> > + };
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + CPU0: cpu@0 {
>
> unit address is wrong.

Sorry am not sure I follow, can you please explain how..

> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x100>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + };
> > +
> > + CPU1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x101>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + };
> > +
> > + CPU2: cpu@2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x102>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + };
> > +
> > + CPU3: cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x103>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + };
> > +
> > + L2_0: l2-cache {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + };
> > + };
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + /* We expect the bootloader to fill in the reg */
>
> Can't you put in a default or base address at least.

Okay will try

--
~Vinod

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