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Subject[PATCH 1/2] dt-bindings: phy: Add Qualcomm Synopsys High-Speed USB PHY binding
Date
From: Sriharsha Allenki <sallenki@codeaurora.org>

It adds bindings for Synopsys 28nm femto phy controller that supports
LS/FS/HS usb connectivity on Qualcomm chipsets.

Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
.../phy/qcom,snps-28nm-usb-hs-phy.txt | 101 ++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt
new file mode 100644
index 000000000000..75e7a09dd558
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt
@@ -0,0 +1,101 @@
+Qualcomm Synopsys 28nm Femto phy controller
+===========================================
+
+Synopsys 28nm femto phy controller supports LS/FS/HS usb connectivity on
+Qualcomm chipsets.
+
+Required properties:
+
+- compatible:
+ Value type: <string>
+ Definition: Should contain "qcom,usb-snps-hsphy".
+
+- reg:
+ Value type: <prop-encoded-array>
+ Definition: USB PHY base address and length of the register map.
+
+- #phy-cells:
+ Value type: <u32>
+ Definition: Should be 0.
+
+- clocks:
+ Value type: <prop-encoded-array>
+ Definition: See clock-bindings.txt section "consumers". List of
+ three clock specifiers for reference, phy core and
+ sleep clocks.
+
+- clock-names:
+ Value type: <string>
+ Definition: Names of the clocks in 1-1 correspondence with the "clocks"
+ property. Must contain "ref", "phy" and "sleep".
+
+- resets:
+ Value type: <prop-encoded-array>
+ Definition: See reset.txt section "consumers". PHY reset specifiers
+ for phy core and POR resets.
+
+- reset-names:
+ Value type: <string>
+ Definition: Names of the resets in 1-1 correspondence with the "resets"
+ property. Must contain "phy" and "por".
+
+- vdd-supply:
+ Value type: <phandle>
+ Definition: phandle to the regulator VDD supply node.
+
+- vdda1p8-supply:
+ Value type: <phandle>
+ Definition: phandle to the regulator 1.8V supply node.
+
+- vdda3p3-supply:
+ Value type: <phandle>
+ Definition: phandle to the regulator 3.3V supply node.
+
+- qcom,vdd-voltage-level:
+ Value type: <prop-array>
+ Definition: This is a list of three integer values <no min max> where
+ each value corresponding to voltage corner in uV.
+
+Optional properties:
+
+- extcon:
+ Value type: <prop-encoded-array>
+ Definition: Should contain the vbus extcon.
+
+- qcom,init-seq:
+ Value type: <u32 array>
+ Definition: Should contain a sequence of <offset value delay> tuples to
+ program 'value' into phy register at 'offset' with 'delay'
+ in us afterwards.
+
+Example:
+
+ phy@7a000 {
+ compatible = "qcom,usb-snps-hsphy";
+ reg = <0x7a000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "phy", "sleep";
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy", "por";
+ vdd-supply = <&vreg_l4_1p2>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ vdda3p3-supply = <&vreg_l12_3p3>;
+ qcom,vdd-voltage-level = <0 1144000 1200000>;
+ qcom,init-seq = <0xc0 0x01 0>,
+ <0xe8 0x0d 0>,
+ <0x74 0x12 0>,
+ <0x98 0x63 0>,
+ <0x9c 0x03 0>,
+ <0xa0 0x1d 0>,
+ <0xa4 0x03 0>,
+ <0x8c 0x23 0>,
+ <0x78 0x08 0>,
+ <0x7c 0xdc 0>,
+ <0x90 0xe0 20>,
+ <0x74 0x10 0>,
+ <0x90 0x60 0>;
+ };
--
2.18.0
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