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SubjectRe: [PATCH v2 3/3] clk: mediatek: Mark bus and DRAM related clocks as critical
Quoting (2018-11-16 10:09:01)
> From: Jasper Mattsson <>
> This marks MUXes axi_sel and ddrphycfg_sel as well as gates
> infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
> Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
> Signed-off-by: Jasper Mattsson <>
> Signed-off-by: Matthias Brugger <>
> ---

Can you add comments in the commit text and in the code about why the
CLK_IS_CRITICAL flag is added to these clks? It makes it easier to
figure out why the flag is there months from now when we all forget

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