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SubjectRe: [PATCH v2 0/7] IP101GR: devicetree based configuration of SEL_INTR32
From: Martin Blumenstingl <>
Date: Sun, 18 Nov 2018 22:23:52 +0100

> The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA
> Ethernet PHY. Due to it's limited amount of pins the RXER (receive
> error) and INTR32 (interrupt) functions share pin 21.

Series applied to net-next, thank you.

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