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    Subject[PATCH 4.18 033/171] ARM: dts: imx6ull: keep IMX6UL_ prefix for signals on both i.MX6UL and i.MX6ULL
    4.18-stable review patch.  If anyone has any objections, please let me know.


    From: Sébastien Szymanski <>

    [ Upstream commit 31edaa6e7fd8143085a6a60c564447c07e76ed9f ]

    Signals available on both i.MX6UL and i.MX6ULL should have the same name
    because it is the case of all others common signals, it avoids to make
    mistakes (use the wrong ones) and it makes writing device tree files
    less complicated. For example:

    pinctrl_uart5: uart5grp {
    fsl,pins = <

    #include <imx6ul.dtsi>
    #include <imx6ul-imx6ull-board.dtsi>

    #include <imx6ull.dtsi>
    #include <imx6ul-imx6ull-board.dtsi>

    Without this patch, the imx6ull-board.dtb will use
    MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX instead of
    MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX and the uart5 will be

    Signed-off-by: Sébastien Szymanski <>
    Reviewed-by: Fabio Estevam <>
    Acked-by: Rob Herring <>
    Signed-off-by: Shawn Guo <>
    Signed-off-by: Sasha Levin <>
    Signed-off-by: Greg Kroah-Hartman <>
    arch/arm/boot/dts/imx6ull-pinfunc.h | 18 +++++++++++++-----
    1 file changed, 13 insertions(+), 5 deletions(-)

    --- a/arch/arm/boot/dts/imx6ull-pinfunc.h
    +++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
    @@ -14,14 +14,23 @@
    * The pin function ID is a tuple of
    * <mux_reg conf_reg input_reg mux_mode input_val>
    +/* signals common for i.MX6UL and i.MX6ULL */
    +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
    +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
    +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
    +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
    +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
    +/* signals for i.MX6ULL only */
    #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
    #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
    #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3
    #define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4
    -#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
    -#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
    -#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
    -#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
    #define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
    #define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
    #define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
    @@ -55,7 +64,6 @@
    #define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
    #define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
    #define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
    -#define MX6ULL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
    #define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
    #define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
    #define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0

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