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SubjectRe: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
On Thu, 15 Nov 2018 11:43:05 +0000
Schrempf Frieder <frieder.schrempf@kontron.De> wrote:

> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> > Hi Frieder,
> >
> > With below patch on top of your v5, Read/Write/Erase on CS1 is working fine for me.
> Ok, are you sure, that AHB read is working too with this patch?
> You are removing the memmap_phy offset from SFAR and the SFXXAD register
> values.
> I can understand that selection of the CS and IP commands will work like
> this, but I can't understand how AHB read should work without the base
> address of the mapped memory.
> I'm afraid I still don't fully understand the background of these
> things,

Same here. Yogesh, can you give us more detail on why you decided to
drop the memmap_phy offset?

> but still thank you for testing.

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