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SubjectRe: [RFC v1 2/7] clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
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On Wed, 2018-11-14 at 23:57 +0100, Martin Blumenstingl wrote:
> The cpu_div3 clock (cpu_in divided by 3) generates a signal with a duty
> cycle of 33%. The CPU clock however requires a clock signal with a duty
> cycle of 50% to run stable.
> cpu_div3 was observed to be problematic when cycling through all
> available CPU frequencies (with additional patches on top of this one)
> while running "stress --cpu 4" in the background. This caused sporadic
> hangs where the whole system would fully lock up.
>
> Amlogic's 3.10 kernel code also does not use the cpu_div3 clock either
> when changing the CPU clock.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> drivers/clk/meson/meson8b.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 40e77fe4ba7c..8a3c346e110d 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -608,20 +608,27 @@ static struct clk_regmap meson8b_cpu_scale_div = {
> },
> };
>
> +static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
> static struct clk_regmap meson8b_cpu_scale_out_sel = {
> .data = &(struct clk_regmap_mux_data){
> .offset = HHI_SYS_CPU_CLK_CNTL0,
> .mask = 0x3,
> .shift = 2,
> + .table = mux_table_cpu_scale_out_sel,
> },
> .hw.init = &(struct clk_init_data){
> .name = "cpu_scale_out_sel",
> .ops = &clk_regmap_mux_ro_ops,
> + /*
> + * NOTE: We are skipping the parent with value 0x2 (which is
> + * "cpu_div3") because it results in a duty cycle of 33% which
> + * makes the system unstable and can result in a lockup of the
> + * whole system.
> + */
> .parent_names = (const char *[]) { "cpu_in_sel",
> "cpu_div2",
> - "cpu_div3",
> "cpu_scale_div" },
> - .num_parents = 4,
> + .num_parents = 3,
> .flags = CLK_SET_RATE_PARENT,
> },
> };

Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>

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