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SubjectRE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Date
Hi Frieder,

With below patch on top of your v5, Read/Write/Erase on CS1 is working fine for me.

I have tested with JFFS2 mounting and booting also for both CS0 and CS1.

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index ce45e8e..4467983 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -490,28 +490,10 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
{
unsigned long rate = spi->max_speed_hz;
int ret, i;
- u32 map_addr;

if (q->selected == spi->chip_select)
return;

- /*
- * In HW there can be a maximum of four chips on two buses with
- * two chip selects on each bus. We use four chip selects in SW
- * to differentiate between the four chips.
- * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
- * the chip we want to access.
- */
- for (i = 0; i < 4; i++) {
- if (i < spi->chip_select)
- map_addr = q->memmap_phy;
- else
- map_addr = q->memmap_phy +
- 2 * q->devtype_data->ahb_buf_size;
-
- qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
- }
-
if (needs_4x_clock(q))
rate *= 4;

@@ -534,7 +516,9 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)

static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
{
- memcpy_fromio(op->data.buf.in, q->ahb_addr, op->data.nbytes);
+ memcpy_fromio(op->data.buf.in,
+ q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
+ op->data.nbytes);
}

static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
@@ -634,7 +618,9 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)

fsl_qspi_select_mem(q, mem->spi);

- qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
+ qspi_writel(q,
+ q->selected * q->devtype_data->ahb_buf_size,
+ base + QUADSPI_SFAR);

qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
@@ -733,6 +719,19 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
base + QUADSPI_BUF3CR);

+ /*
+ * In HW there can be a maximum of four chips on two buses with
+ * two chip selects on each bus. We use four chip selects in SW
+ * to differentiate between the four chips.
+ * We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+ * the chip we want to access.
+ */
+
+ qspi_writel(q, q->devtype_data->ahb_buf_size, base + QUADSPI_SFA1AD);
+ qspi_writel(q, q->devtype_data->ahb_buf_size * 2 , base + QUADSPI_SFA2AD);
+ qspi_writel(q, q->devtype_data->ahb_buf_size * 3 , base + QUADSPI_SFB1AD);
+ qspi_writel(q, q->devtype_data->ahb_buf_size * 4 , base + QUADSPI_SFB2AD);
+
q->selected = -1;

--
Regards
Yogesh Gaur

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