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SubjectRe: [PATCH 4/7] node: Add memory caching attributes
On 11/14/18 2:49 PM, Keith Busch wrote:
> System memory may have side caches to help improve access speed. While
> the system provided cache is transparent to the software accessing
> these memory ranges, applications can optimize their own access based
> on cache attributes.
> In preparation for such systems, provide a new API for the kernel to
> register these memory side caches under the memory node that provides it.
> The kernel's sysfs representation is modeled from the cpu cacheinfo
> attributes, as seen from /sys/devices/system/cpu/cpuX/cache/. Unlike CPU
> cacheinfo, though, a higher node's memory cache level is nearer to the
> CPU, while lower levels are closer to the backing memory. Also unlike
> CPU cache, the system handles flushing any dirty cached memory to the
> last level the memory on a power failure if the range is persistent.
> The exported attributes are the cache size, the line size, associativity,
> and write back policy.

Could you also include an example of the layout?

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