Messages in this thread |  | | From | "Moger, Babu" <> | Subject | Re: [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD | Date | Wed, 3 Oct 2018 17:21:18 +0000 |
| |
Hi Reinette,
On 10/02/2018 05:13 PM, Reinette Chatre wrote: > Hi Babu, > > On 9/24/2018 12:19 PM, Moger, Babu wrote: >> +/* >> + * Check whether a cache bit mask is valid. AMD allows >> + * non-contiguous masks. >> + */ >> +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) >> +{ >> + unsigned long first_bit, zero_bit, val; >> + unsigned int cbm_len = r->cache.cbm_len; >> + int ret; >> + >> + ret = kstrtoul(buf, 16, &val); >> + if (ret) { >> + rdt_last_cmd_printf("non-hex character in mask %s\n", buf); >> + return false; >> + } >> + >> + if (val == 0 || val > r->default_ctrl) { >> + rdt_last_cmd_puts("mask out of range\n"); >> + return false; >> + } > > According to > https://www.amd.com/system/files/TechDocs/56375_Quality_of_Service_Extensions.pdf > "If an L3_MASK_n register is programmed with all 0’s, that COS will be > prevented from allocating any lines in the L3 cache." > > The "val == 0" test thus does not seem necessary.
Yes. Good point. We don't need this test. > >> + >> + first_bit = find_first_bit(&val, cbm_len); >> + zero_bit = find_next_zero_bit(&val, cbm_len, first_bit); >> + >> + >> + if ((zero_bit - first_bit) < r->cache.min_cbm_bits) { >> + rdt_last_cmd_printf("Need at least %d bits in mask\n", >> + r->cache.min_cbm_bits); >> + return false; >> + } > > If AMD platforms accept CBM of all zeroes then it seems that the > platforms would not require a minimum number of set bits?
Yes. We don't need this check as well. Tested and confirmed. Thanks > > Reinette >
|  |