Messages in this thread |  | | Date | Wed, 3 Oct 2018 17:49:37 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont |
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On Wed, Oct 03, 2018 at 05:41:32PM +0200, Peter Zijlstra wrote: > On Wed, Oct 03, 2018 at 08:10:31AM +0200, Thomas Gleixner wrote: > > On Tue, 2 Oct 2018, kan.liang@linux.intel.com wrote: > > > > There is another variant of model/stepping micro code verification code in > > intel_snb_pebs_broken(). Can we please make this table based and use a > > common function? That's certainly not the last quirk we're going to have. > > > > We already have a table based variant of ucode checking in > > bad_spectre_microcode(). It's trivial enough to generalize that. > > apic_check_deadline_errata() is another one. That one already uses the > x86_cpu_id thing, but still plays silly games for steppings. So if we're > going to build a new microcode table matcher...
intel_snb_pebs_broken() looks like a potential candidate too...
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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