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SubjectRe: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont
> There is another variant of model/stepping micro code verification code in
> intel_snb_pebs_broken(). Can we please make this table based and use a
> common function? That's certainly not the last quirk we're going to have.

I have a patch to add a table driven microcode matcher for another fix.
Will post shortly.


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