Messages in this thread |  | | From | "Liang, Kan" <> | Subject | Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont | Date | Wed, 3 Oct 2018 09:32:58 -0400 |
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On 10/3/2018 2:10 AM, Thomas Gleixner wrote: > On Tue, 2 Oct 2018, kan.liang@linux.intel.com wrote: >> +static bool intel_atom_v4_counter_freezing_broken(int cpu) >> { >> u32 rev = UINT_MAX; /* default to broken for unknown stepping */ >> >> - switch (cpu_data(cpu).x86_stepping) { >> - case 1: >> - rev = 0x28; >> + switch (cpu_data(cpu).x86_model) { >> + case INTEL_FAM6_ATOM_GOLDMONT: >> + switch (cpu_data(cpu).x86_stepping) { >> + case 2: >> + rev = 0xe; >> + break; >> + case 9: >> + rev = 0x2e; >> + break; >> + case 10: >> + rev = 0x8; >> + break; >> + } >> break; >> - case 8: >> - rev = 0x6; >> + >> + case INTEL_FAM6_ATOM_GOLDMONT_X: >> + switch (cpu_data(cpu).x86_stepping) { >> + case 1: >> + rev = 0x1a; >> + break; >> + } >> break; >> + >> + case INTEL_FAM6_ATOM_GOLDMONT_PLUS: >> + switch (cpu_data(cpu).x86_stepping) { >> + case 1: >> + rev = 0x28; >> + break; >> + case 8: >> + rev = 0x6; >> + break; >> + } >> } >> >> return (cpu_data(cpu).microcode < rev); > > There is another variant of model/stepping micro code verification code in > intel_snb_pebs_broken(). Can we please make this table based and use a > common function? That's certainly not the last quirk we're going to have. > > We already have a table based variant of ucode checking in > bad_spectre_microcode(). It's trivial enough to generalize that. >
Sure, I will generalize the bad_spectre_microcode(), rename it to is_bad_intel_microcode(), and move it to arch\x86\kernel\cpu\microcode\intel.c. The spectre code and perf code will share the generalized function.
Thanks, Kan
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