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SubjectRe: [PATCH v9 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore
Hello Dave,

On Mon, Oct 01, 2018 at 07:05:11AM -0700, Dave Hansen wrote:
> On 10/01/2018 06:16 AM, Gautham R. Shenoy wrote:
> >
> > Patch 3: Creates a pair of sysfs attributes named
> > /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings
> > and
> > /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings_list
> > exposing the small-core siblings that share the L1 cache
> > to the userspace.
> I really don't think you've justified the existence of a new user/kernel
> interface here. We already have information about threads share L1
> caches in here:
> /sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list

Hmmm. My bad, I wasn't aware of this sysfs interface. We can use this
to share information about L1 cache. And currently on the upstream
kernel we report incorrect value on POWER9 SMT8 core. I will fix
this. Thanks for calling this out.

> The only question would be if anything would break because it assumes
> that all SMT siblings share all caches. But, it breaks if your new
> interface is there or not; it's old software that we care about.

Up until POWER9 SMT8 cores, this assumption was true that all SMT
siblings share all caches. POWER9 SMT8 cores are the only exception.

Thanks and Regards

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