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Subject[PATCH v2 5/5] arm64: dts: qcom: sdm845: Add USB PHY lane two
Date
This change adds the second lane registers for the USB PHY, now that the
QMP phy bindings have been updated. This way the driver can stop
reaching beyond its register region to get at the second lane.

Signed-off-by: Evan Green <evgreen@chromium.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9c72edb678ec..f28c50e93f5a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1188,10 +1188,12 @@
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";

- usb_1_ssphy: lane@88e9200 {
+ usb_1_ssphy: lanes@88e9200 {
reg = <0x88e9200 0x128>,
<0x88e9400 0x200>,
<0x88e9c00 0x218>,
+ <0x88e9600 0x128>,
+ <0x88e9800 0x200>,
<0x88e9a00 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
@@ -1219,10 +1221,12 @@
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";

- usb_2_ssphy: lane@88eb200 {
+ usb_2_ssphy: lanes@88eb200 {
reg = <0x88eb200 0x128>,
<0x88eb400 0x1fc>,
<0x88eb800 0x218>,
+ <0x88eb600 0x128>,
+ <0x88eb800 0x1fc>,
<0x88e9600 0x70>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
--
2.16.4
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