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SubjectRe: [PATCH v2 2/2] clk: tegra20: Enable lock-status polling for PLLs
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On 8/31/18 12:45 PM, Dmitry Osipenko wrote:
> On 8/31/18 12:29 PM, Peter De Schrijver wrote:
>> On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
>>> Currently all PLL's on Tegra20 use a hardcoded delay despite of having
>>> a lock-status bit. The lock-status polling was disabled ~7 years ago
>>> because PLLE was failing to lock and was a suspicion that other PLLs
>>> might be faulty too. Other PLLs are okay, hence enable the lock-status
>>> polling for them. This reduces delay of any operation that require PLL
>>> to lock.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> ---
>>>
>>> Changelog:
>>>
>>> v2: Don't enable polling for PLLE as it known to not being able to lock.
>>>
>>
>> This isn't correct. The lock bit of PLLE can declare lock too early, but the
>> PLL itself does lock.
>
> Indeed, it locks but can't be polled for the lock-status as it doesn't have the
> lock-status bit.

Actually it has lock-status bit. Not sure how I managed to miss it before.

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